Self-aligned contacts for nanosheet field effect transistor devices
US11462443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2020 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Feb 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact mater…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.