Semiconductor packages including a recessed conductive post
US11462462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2020 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Feb 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.