LDMOS transistor having vertical floating field plate and manufacture thereof

US11462640B2 · kind B2 · utility

Assignee

• SiEn (QingDao) Integrated Circuits Co., Ltd. · CN

Inventors

• Min-hwa Chi · Palo Alto, US
• Min Li · Qingdao, CN

Key dates

• Filing date: Sep 7, 2021
• Grant date: Oct 4, 2022
• Expiry date: Sep 7, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

The present application provides a LDMOS transistor having a floating vertical field plate (VFP) and a manufacturing method thereof. The floating VFP comprises a floating field plate polysilicon layer and a laminated structure. The laminated structure comprises a stack of alternate layers of insulating material and ferroelectric material, and in the laminated structure, an outermost layer and an innermost layer are the insulating material. In the present application, the polarization in the ferroelectric material is set in the floating VFP with smaller size, the polarization of the ferroelectric layer enhances the “charge sharing” effect to produce higher breakdown voltage when the transistor is off; and the polarization of the ferroelectric material layer induces more electrons in the drift zone to reduce on resistance when the transistor is on. Accordingly, the increase of breakdown voltage and the reduction of on resistance can be achieved simultaneously.