Asynchronous pipeline merging using long vector arbitration
US11467845B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Apr 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for asynchronous pipeline merging are described herein. An apparatus, includes a memory controller, which includes merge circuitry; where the memory controller chiplet is configured to perform operations including those to: perform a bitwise logical operation on a first logging bit vector and a second logging bit vector to obtain a result vector, wherein the first logging bit vector is associated with a first pipeline and the second logging bit vector is associated with a second pipeline, and wherein bits in respective index positions of the first and second logging bit vectors represent transactions; select a completed transaction from the result vector using a round-robin technique; and forward the completed transaction from the set of completed transactions to an output pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.