Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping
US11467932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jan 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.