Memory system capable of improving stability of a data read operation of interface circuit, and method of operating the memory system
US11468921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jun 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.