Etching method
US11469095B2 · kind B2 · utility
0Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2019 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.