Pierre Bar
26Patents
3h-index
17Co-inventors
56Inventor score
Filing activity: Oct 1, 2010 → Sep 8, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8841748B2 | Semiconductor device comprising a capacitor and an electrical connection via and fabrication method | Electricity | 17 | Active |
| US8841749B2 | Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method | Electricity | 16 | Active |
| US9638589B2 | Method for determining a three-dimensional stress field of an object, an integrated structure in particular, and corresponding system | Electricity | 3 | Active |
| US8397360B2 | Method for manufacturing a monolithic oscillator with bulk acoustic wave (BAW) resonators | Emerging Cross-Sectional Technologies | 3 | Active |
| US8593234B2 | Bragg mirror and BAW resonator with a high quality factor on the bragg mirror | Emerging Cross-Sectional Technologies | 2 | Active |
| US8756778B2 | Method of adjustment during manufacture of a circuit having a capacitor | Emerging Cross-Sectional Technologies | 2 | Active |
| US9240624B2 | Process for fabricating an integrated circuit comprising at least one coplanar waveguide | Electricity | 2 | Active |
| US8587921B2 | Method of adjustment on manufacturing of a circuit having a resonant element | Emerging Cross-Sectional Technologies | 2 | Active |
| US9418954B2 | Integrated circuit chip assembled on an interposer | Electricity | 1 | Active |
| US9780015B2 | Integrated circuit chip assembled on an interposer | Electricity | 0 | Active |
| US9385424B2 | Three-dimensional integrated structure comprising an antenna | Electricity | 0 | Active |
| US10770306B2 | Method of etching a cavity in a stack of layers | Physics | 0 | Active |
| US9147725B2 | Semiconductor device comprising an integrated capacitor and method of fabrication | Electricity | 0 | Active |
| US9647625B2 | Method for manufacturing BAW resonators on a semiconductor wafer | Emerging Cross-Sectional Technologies | 0 | Active |
| US9646914B2 | Process for producing a microfluidic circuit within a three-dimensional integrated structure, and corresponding structure | Electricity | 0 | Active |
| US8704358B2 | Method for forming an integrated circuit | Electricity | 0 | Active |
| US9455191B2 | Shielded coplanar line | Electricity | 0 | Active |
| US12347670B2 | Etching method | Electricity | 0 | Active |
| US11469095B2 | Etching method | Electricity | 0 | Active |
| US8975737B2 | Transmission line for electronic circuits | Electricity | 0 | Active |
| US9324612B2 | Shielded coplanar line | Electricity | 0 | Active |
| US8988893B2 | Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device | Emerging Cross-Sectional Technologies | 0 | Active |
| US9673088B2 | Process for fabricating an integrated circuit comprising at least one coplanar waveguide | Electricity | 0 | Active |
| US8994172B2 | Connection of a chip provided with through vias | Electricity | 0 | Active |
| US9165861B2 | Process for producing at least one through-silicon via with improved heat dissipation, and corresponding three-dimensional integrated structure | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.