Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

US11469299B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Biswajeet Guha · Hillsboro, US
• Dax M. Crum · Beaverton, US
• Patrick H. Keys · Portland, US
• Tahir Ghani · Portland, US
• Susmita Ghose · Mountain View, US
• Ted COOK, JR. · Hillsboro, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Oct 11, 2022
• Expiry date: Feb 11, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.