Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus
US11469770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jan 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.