High bandwidth CDR
US11469877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Aug 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.