Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation
US11475191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2019 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.