Memory cell arrangement and methods thereof
US11475935B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jun 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2277
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various aspects relate to a memory cell arrangement including: a memory cell including a field-effect transistor structure and a spontaneous-polarizable memory layer; and a control circuit configured to cause a writing of the memory cell by a writing operation, the writing operation including: carrying out a writing sequence including: supplying a write signal set to the memory cell to provide a write voltage drop to bring a threshold voltage of the memory cell into a target range by polarizing the memory layer, and, subsequently, supplying a post-conditioning signal set to the memory cell to provide a post-conditioning voltage drop having opposite polarity with respect to the write voltage drop to change the threshold voltage by partially depolarizing the memory layer; and checking whether the threshold voltage is in the target range, and repeating the writing sequence in the case that the threshold voltage is not in the target range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.