Decoding architecture for memory tiles
US11475947B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Apr 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.