Computing array based on 1T1R device, operation circuits and operating methods thereof
US11475949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Oct 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.