Three-dimensional packaging techniques for power FET density improvement
US11476232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging technology in which power switching elements, such as field-effect transistors (FETs), can be oriented in a vertical position relative to the printed circuit board (PCB) on which the product is mounted. The power die including the switching element(s) can essentially stand “on end” so that they take up very little PCB area. Multiple dies can be positioned this way, and the dies can be attached to a heat sink structure, which is designed to take the heat generated by the dies onto the top of the package. The heat sink structure can be attached to a structure to route the power and analog signals properly to the desired pins/leads/balls of the finished product. Using these techniques can result in a significant increase in the power density (both PCB space and solution volume) of power switching elements, e.g., FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.