Manufacturing method of chip package
US11476293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Nov 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/805
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.