Successive approximation register using switched unit elements
US11476866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Feb 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.