Computing device with independently coherent nodes
US11481116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Nov 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device comprises two or more compute nodes, that each include two or more processor cores. Each compute node comprises an independently coherent domain that is not coherent with other compute nodes. A central IO die is communicatively coupled to each of the two or more compute nodes. A plurality of natively-attached volatile memory units are attached to the central IO die via one or more memory controllers. The central IO die includes one or more home agents for each compute node. The home agents are configured to map memory access requests received from the compute nodes to one or more addresses within the natively attached volatile memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.