Memory with programmable die refresh stagger
US11482271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Apr 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.