Method for manufacturing semiconductor structure
US11482445B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Jun 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for manufacturing a semiconductor structure having different filling layers. The method includes forming a multi-layer stack in a semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second layer, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias. The method further includes recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.