Substrate defect blocking layers for strained channel semiconductor devices
US11482457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2017 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.