Hardware efficient decision feedback equalization training
US11483185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.