Aaron Willey
48Patents
6h-index
17Co-inventors
62Inventor score
Filing activity: Aug 25, 2009 → Dec 12, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8643418B2 | Apparatus and methods for altering the timing of a clock signal | Electricity | 32 | Active |
| US10056909B1 | Single-lock delay locked loop with cycle counter and method therefore | Physics | 14 | Active |
| US8897063B2 | Multilevel differential sensing in phase change memory | Physics | 12 | Active |
| US8283950B2 | Delay lines, amplifier systems, transconductance compensating systems and methods of compensating | Electricity | 11 | Active |
| US9036408B1 | Phase change memory with bit line matching | Physics | 9 | Active |
| US8436670B2 | Power supply induced signal jitter compensation | Electricity | 7 | Active |
| US8729941B2 | Differential amplifiers, clock generator circuits, delay lines and methods | Electricity | 6 | Active |
| US8648635B2 | Clock signal generators having a reduced power feedback clock path and methods for generating clocks | Electricity | 5 | Active |
| US9225319B2 | Apparatus and methods for altering the timing of a clock signal | Electricity | 5 | Active |
| US8461889B2 | Clock signal generators having a reduced power feedback clock path and methods for generating clocks | Electricity | 4 | Active |
| US11803437B1 | Write hardware training acceleration | Physics | 4 | Active |
| US8493104B2 | Clock signal generators having a reduced power feedback clock path and methods for generating clocks | Electricity | 4 | Active |
| US8830741B1 | Phase change memory with flexible time-based cell decoding | Physics | 4 | Active |
| US8373462B2 | Delay lock loop and delay lock method | Electricity | 3 | Active |
| US10848352B1 | Time based feed forward equalization (TFFE) for high-speed DDR transmitter | Physics | 3 | Active |
| US7944300B2 | Bias circuit and amplifier providing constant output current for a range of common mode inputs | Electricity | 3 | Active |
| US8779822B2 | Power supply induced signal jitter compensation | Electricity | 2 | Active |
| US10545889B1 | High-speed low VT drift receiver | Electricity | 2 | Active |
| US8427204B2 | Mixed-mode input buffer | Electricity | 2 | Active |
| US8604850B2 | Measurement initialization circuitry | Electricity | 2 | Active |
| US10250265B2 | Single-lock delay locked loop with cycle counter and method therefor | Physics | 2 | Active |
| US11483185B1 | Hardware efficient decision feedback equalization training | Electricity | 2 | Active |
| US10545895B1 | Auto-zeroing receiver for memory interface devices | Physics | 2 | Active |
| US8829882B2 | Current generator circuit and method for reduced power consumption and fast response | Physics | 1 | Active |
| US8947141B2 | Differential amplifiers, clock generator circuits, delay lines and methods | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.