Semiconductor storing apparatus and flash memory operation method
US11487343B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2020 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.