Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods
US11487545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Mar 4, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor branch prediction circuit employs back-invalidation of prediction cache entries based on decoded branch instructions. The execution information of a previously executed branch instruction is obtained from a prediction cache entry and compared to generated decode information in an instruction decode circuit. Execution information of branch instructions stored in the prediction cache entry is updated in response to a mismatch of the execution information and the decode information of the branch instruction. Existing branch prediction circuits invalidate prediction cache entries of a block of instructions when the block of instructions is invalidated in an instruction cache. As a result, valid branch instruction execution information may be unnecessarily discarded. Updating prediction cache entries in response to a mismatch of the execution information and the decode information of the branch instruction maintains the execution information in the prediction cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.