Richard W. Doing
27Patents
8h-index
51Co-inventors
78Inventor score
Filing activity: Dec 22, 1997 → Dec 5, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6018759A | Thread switch tuning tool for optimal performance in a computer processor | Physics | 109 | Expired |
| US6438671B1 | Generating partition corresponding real address in partitioned mode supporting system | Physics | 101 | Expired |
| US7779232B2 | Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches | Physics | 62 | Active |
| US6161166A | Instruction cache for multithreaded processor | Physics | 54 | Expired |
| US6993640B2 | Apparatus for supporting a logically partitioned computer system | Physics | 33 | Expired |
| US7707396B2 | Data processing system, processor and method of data processing having improved branch target address cache | Physics | 20 | Active |
| US6829684B2 | Applications of operating mode dependent error signal generation upon real address range checking prior to translation | Physics | 17 | Expired |
| US8131976B2 | Tracking effective addresses in an out-of-order processor | Physics | 15 | Active |
| US9715411B2 | Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system | Physics | 6 | Active |
| US7281120B2 | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor | Physics | 5 | Expired |
| US7305586B2 | Accessing and manipulating microprocessor state | Physics | 5 | Expired |
| US7934081B2 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness | Physics | 5 | Active |
| US8127115B2 | Group formation with multiple taken branches per group | Physics | 5 | Active |
| US7836287B2 | Reducing the fetch time of target instructions of a predicted taken branch instruction | Physics | 4 | Active |
| US8386712B2 | Structure for supporting simultaneous storage of trace and standard cache lines | Physics | 3 | Active |
| US7644233B2 | Apparatus and method for supporting simultaneous storage of trace and standard cache lines | Physics | 3 | Active |
| US7610449B2 | Apparatus and method for saving power in a trace cache | Emerging Cross-Sectional Technologies | 1 | Active |
| US8015565B2 | Preventing livelocks in processor selection of load requests | Physics | 1 | Active |
| US7437543B2 | Reducing the fetch time of target instructions of a predicted taken branch instruction | Physics | 1 | Expired |
| US7996618B2 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness | Physics | 1 | Active |
| US7711930B2 | Apparatus and method for decreasing the latency between instruction cache and a pipeline processor | Physics | 1 | Active |
| US7321954B2 | Method for software controllable dynamically lockable cache line replacement system | Physics | 1 | Expired |
| US11487545B2 | Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods | Physics | 0 | Active |
| US8479184B2 | General purpose emit for use in value profiling | Physics | 0 | Active |
| US12086600B2 | Branch target buffer with shared target bits | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.