Separating parity data from host data in a memory sub-system
US11487609B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 14, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Jul 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory device including a first unit, and a processing device, operatively coupled to the memory device, to perform operations including identifying a set of parity data on a volatile memory, determining whether the set of parity data satisfies a condition pertaining to a size of the set of parity data, and responsive to determining that the set of parity data does not satisfy the condition, appending parity data to the set of parity data. The parity data is generated based on a set of host data written on the first unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.