Semiconductor memory devices and methods of operating semiconductor memory devices
US11487615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Apr 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.