Adiabatic flip-flop and memory cell design
US11488660B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | May 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.