Concurrent multi-bit access in cross-point array
US11488662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2020 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Nov 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.