Method for fabricating high-voltage (HV) transistor
US11488837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Jan 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.