Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial
US11489544B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | May 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.