Patent · US Active

Method and system for improving rock bottom sleep current of processor memories

US11493986B2 · kind B2 · utility

0Cited by

4References

28Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Bharat Kumar Rangarajan · Bengaluru, IN
Rajesh Arimilli · Bengaluru, IN
Srinivas Turaga · Kanchinakote, IN

Key dates

Filing date	Dec 22, 2019
Grant date	Nov 8, 2022
Priority date	—
Expiry date	Dec 22, 2039

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.