Tiling format for convolutional neural networks
US11494592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Sep 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.