Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method
US11495288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2021 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Jan 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.