Three-dimensional semiconductor memory device
US11495615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Apr 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.