Multi-tier three-dimensional memory device with dielectric support pillars and methods for making the same
US11495616B2 · kind B2 · utility
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23References
5Claims
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Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a semiconductor material layer, a memory opening and a support opening extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a semiconductor material portion in contact with the semiconductor material layer, and a support pillar structure located in the support opening. The support pillar structure lacks a semiconductor material portion which is in contact with the semiconductor material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.