Flip-flop circuit with glitch protection
US11496120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2021 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Jan 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.