Memory cell for dot product operation in compute-in-memory chip
US11500960B2 · kind B2 · utility
1Cited by
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14Claims
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Key dates
| Filing date | Oct 29, 2019 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Mar 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.