Pre-silicon chip model of extracted workload inner loop instruction traces
US11501046B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Mar 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided to validate a computer processor. The system includes a computing system configured to obtain core dump data including executable instructions corresponding to a code stored in a legacy processor. An instruction-level simulator is installed in the computing system and is configured to simulate the executable instructions to generate a plurality of instruction traces. The system further includes a pre-silicon chip model simulator configured to execute the instruction traces to generate performance data. The computer processor is verified based at least in part on the performance data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.