Inventor · Austin, TX, US

Nelson Wu

14Patents

2h-index

5Co-inventors

39Inventor score

Filing activity: Aug 12, 2017 → Feb 23, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US10169186B1	Efficient testing of direct memory address translation	Physics	3	Active
US10169185B1	Efficient testing of direct memory address translation	Physics	2	Active
US10521355B2	Method, system, and apparatus for stress testing memory translation tables	Physics	1	Active
US11094391B2	List insertion in test segments with non-naturally aligned data boundaries	Physics	0	Active
US10438682B2	List insertion in test segments with non-naturally aligned data boundaries	Physics	0	Active
US11061821B2	Method, system, and apparatus for stress testing memory translation tables	Physics	0	Active
US10481991B2	Efficient testing of direct memory address translation	Physics	0	Active
US10489261B2	Efficient testing of direct memory address translation	Physics	0	Active
US12118355B2	Cache coherence validation using delayed fulfillment of L2 requests	Physics	0	Active
US11501046B2	Pre-silicon chip model of extracted workload inner loop instruction traces	Physics	0	Active
US11620235B1	Validation of store coherence relative to page translation invalidation	Physics	0	Active
US10748637B2	System and method for testing processor errors	Physics	0	Active
US12130749B2	Validation of store coherence relative to page translation invalidation	Physics	0	Active
US12141071B2	Performance and reliability of processor store operation data transfers	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.