Non-volatile memory die with on-chip data augmentation components for use with machine learning
US11501109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2019 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jul 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components of the die to generate augmented versions of images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device. Other aspects relate to configuring under-the-array or next-to-the-array components of the die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of a NAND array to inject noise into the images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.