Selective metal deposition by patterning direct electroless metal plating
US11501967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2019 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Mar 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1173
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.