Hybrid wafer bonding method and structure thereof
US11502058B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80896
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first substrate, a first dielectric, and a first via structure. The first via structure includes a first contact via and first metal impurities doped in the first contact via. The second semiconductor structure includes a second substrate, a second dielectric layer, and a second via structure. The second via structure includes a second contact via and second metal impurities doped in the second contact via. The method further includes bonding the first semiconductor structure with the second semiconductor and forming a self-barrier layer by an alloying process. The self-barrier layer is formed by a multi-component oxide corresponding to the first and second metal impurities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.