Three-dimensional semiconductor memory device
US11502084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Aug 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.