Layout pattern of static random access memory and the manufacturing method thereof

US11502088B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Wei-Chi Lee · Tainan, TW
• Shu-Wei Yeh · Taichung, TW
• Chang-Hung Chen · Tainan, TW

Key dates

• Filing date: Feb 1, 2021
• Grant date: Nov 15, 2022
• Expiry date: Apr 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.