Low-cost and low-voltage anti-fuse array
US11502090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2021 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jul 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.