Vertical power semiconductor device, semiconductor wafer or bare-die arrangement, carrier, and method of manufacturing a vertical power semiconductor device
US11502190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jan 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 μm to 200 μm. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 μm to 5 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.