Extended-drain metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer
US11502193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Nov 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, and a gate electrode is formed over the substrate. The gate electrode has a sidewall, and the gate electrode is laterally positioned between the first source/drain region and the second source/drain region. A buffer dielectric layer is formed that includes a first dielectric layer having a first portion positioned between the substrate and the gate electrode. The dielectric layer also has a second portion positioned on the substrate laterally between the sidewall of the gate electrode and the first source/drain region. The first portion of the dielectric layer has a first thickness, and the second portion of the first dielectric layer has a second thickness that is less than the first thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.